1. Field of the Invention
The invention relates to flip-flops, and more particularly to flip-flops receiving low swing clock signals.
2. Description of the Related Art
A flip-flop is a circuit that has two stable states and can be used to store state information. The two stable states of a flip-flop respectively represent values “0” and “1”. A flip-flop is usually controlled by a clock signal. Clocking causes the flip-flop to either change or retain its output signal based upon the values of input signals at a transition. Some flip-flops change output on a rising edge of the clock signal, others on the falling edge of the clock signal.
Referring to FIG. 1, a circuit diagram of a conventional flip-flop 200 is shown. A conventional flip-flop 200 may include inverters 231, 232, 233, and 234, passing gate circuits 202 and 206, and latch circuits 204 and 208. A high swing clock signal CK is fed to an inverter 251. The inverter 251 inverts the high swing clock signal CK to generate an inverted clock signal CKB, and an inverter 253 then inverts the inverted clock signal CKB to generate a clock signal CK1.
The latch circuit 204 includes two inverters 213 and 214 and a transmission gate including PMOS transistor 215 and an NMOS transistor 216. The latch circuit 208 includes two inverters 223 and 224 and a transmission gate including a PMOS transistor 225 and an NMOS transistor 226. The inverter 231 inverts a data signal to generate an inverted data signal. When the clock signal CK1 is at a logic low level and the inverted clock signal CKB is at a logic high level, the passing gate circuit 202 passes the inverted data signal to a node 217 of the latch circuit 204, the transmission gate including transistors 215 and 216 cuts off the feedback path of the latch circuit 204, the passing gate circuit 206 is off, and the transmission gate including transistors 225 and 226 retains/builds the feedback path of the latch circuit 208. Then the latch circuit 204 receives the inverted data signal from the node 217, and inverts the inverted data signal to generate a data signal on a node 218. When the inverted clock signal CKB is at a logic low level and the clock signal CK1 is at a logic high level, the passing gate circuit 202 is off, the transmission gate including transistors 215 and 216 retains/builds the feedback path of the latch circuit 204 the passing gate circuit 206 passes the data signal from the node 218 to a node 227 of the latch circuit 208, and the transmission gate including transistors 225 and 226 cuts off the feedback path of the latch circuit 208. The latch circuit 208 receives the data signal from the node 227, and inverts the data signal to generate an inverted data signal on a node 228. The inverter 232 then inverts the inverted data signal to generate a data signal on an output node Q, and the inverters 233 and 234 deliver the inverted data signal to an inverted output node QB.
Oscillation of a clock signal induces power consumption. If a clock signal of a circuit oscillates with a low swing voltage, the power consumption of the circuit is reduced by a great level. Because portable devices have a limited amount of power resources, power consumption reduction is important for portable devices. The clock signals used in circuits with limited power resources therefore are designed to have a low swing level for power consumption reduction. The conventional flip-flop 200, however, cannot directly receive a low swing clock signal. The passing gate circuits 202 and 206 respectively include PMOS transistors 211 and 221 having gates coupled to clock signals CK1 and CKB, and the latch circuits 204 and 208 also include PMOS transistors 215 and 225 having gates coupled to clock signals CKB and CK1. If the clock signals CK1 and CKB are low swing clock signals, the PMOS transistors 211, 215, 221, and 225 cannot be completely turned off by the low voltage of the clock signals. The conventional flip-flop 200 therefore cannot normally operate with a low swing clock signal. The voltage level of the low swing clock signals therefore must be amplified with low-to-high level shifters before the low swing clock signals are fed to conventional flip-flops. The level shifters increase manufacturing cost of a circuit. If new flip-flops capable of receiving a low swing clock signal are used in the circuit, the low-to-high level shifters can be omitted to reduce the manufacturing cost of the circuit. Thus, new flip-flops capable of receiving low swing clock signals are required.